https://developer.arm.com/documentation/107630/latest/
随着近年来Arm服务器的应用越来越，越来越多的云厂商开始提供基于Arm架构的云实例，越来越多的开发人员正在为Arm平台编写软件。
Synchronization是软件迁移和优化过程中的热门话题。基于Arm架构的服务器通常具有比其架构更多的CPU内核，对Synchronization的深入理解显得更为重要。
Arm和X86 CPU之间最显著的区别是内存模型：Arm架构具有与x86架构的TSO（Total Store Order）模型不同的弱内存模型。不同的内存模型可能会导致程序在架构上运行良好，但在另架构上会遇到性能问题或错误。Arm服务器更宽松的内存模型允许更多的编译器和硬件优化以提高系统性能，但代价是更难理解并且可能更容易编写错误代码。
我们创作此文档是为了分享有关Arm架构的Synchronization专业知识，可以帮助其架构的开发人员在Arm系统上进行开发。
本文档首先介绍了Armv8-A架构上的Synchronization相关知识，包括原子操作、Arm内存顺序和数据访问屏障指令。
锁的实现要求原子访问，Arm架构定义了两种类型的原子访问：
Load exclusive and store exclusive
AtomIC operation, whICh is introduced in armv8.1-a large system extension (LSE)
LDREX/LDXR - The load exclusive instruction performs a load from an addressed memory location, the PE (e.g. the CPU) also marks the physical address being accessed as an exclusive access. The exclusive access mark is checked by store exclusive instructions.STREX/STXR - The store exclusive instruction tries to a value from a register to memory if the PE (e.g. the CPU) has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.
LDXR/STXR使用了try and test机制，LSE不一样，直接强制原子访问，主要有如下指令:
Compare and Swap instructions, CAS, and CASP. These instructions perform a read from memory and compare it against the value held in the first register. If the comparison is equal, the value in the second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.
Atomic memory operation instructions, LD
Swap instruction, SWP. This instruction atomically reads a location from memory into a register and writes back a different supplied value back to the same memory location.
Arm架构定义了弱内存模型，内存访问可能不会按照代码顺序：
Arm架构定义了屏障指令来保证内存访问的顺序。 DMB – Data Memory Barrier
LDR X0, [X1] ;Must be seen by memory system before STR DMB SY ADD X2, #1 ; May be executed before or after memory system sees LDR STR X3, [X4] ;Must be seen by memory system after LDRUse a DSB when necessary, but do not overuse them
All explicit memory accesses before the DSB in program order have completed
Any outstanding cache/TLB/branch predictor operations complete
DC ISW ; Operation must have completed before DSB can complete STR X0, [X1] ; Access must have completed before DSB can complete DSB SY ADD X2, X2, #3 ;Cannot be executed until DSB completesAll accesses after the LDAR are observed by memory system after the LDAR.
Accesses before the LDAR are not affected.
All accesses before the STLR are observed by memory system before the STLR
Accesses after the STLR are not affected
有了语言层面的内存模型，对于大多数情况，开发者不需要去写依赖于具体架构的汇编代码，而只需要借助于良好设计的语言层面的内存模型来编写高质量代码，不必担心架构差异。
在白皮书中，为帮助读者更好地理解，我们选取了三个典型案例进行深入分析。由于与Synchronization相关的编程非常复杂，因此我们必须仔细权衡其正确性和性能。我们建议首先使用较重的屏障指令保证逻辑的正确性，然后通过移除一些冗余屏障或在必要时切换到较轻的屏障来继续提高性能。对Arm内存模型和相关指令的深入理解，是对实现准确和高性能的Synchronization编程非常有必要的。 在附录部分，我们还介绍了内存模型工具（The litmus test suite），可以帮助理解内存模型并在各种架构上验证程序。 关于以上内容更完整的讲解，请参考“Arm架构下的Synchronization概述和案例分析白皮书”。
Arm, “Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile Documentation”
https://developer.arm.com/docs/ddi0487/latest
“The software suite diy7”
http://diy.inria.fr/
